cystech electronics corp. spec. no. : c140e3 issued date : 2015.12.09 revised date : page no. : 1/ 8 mtd07n04e3 cystek product specification n-channel enhancement mode power mosfet mtd07n04e3 bv dss 40v 58a i d @v gs =10v, t c =25 c 13.4a i d @v gs =10v, t a =25 c r ds(on) @v gs =10v, i d =20a 5.1 m (typ) features r ds(on) @v gs =4.5v, i d =10a ? low on resistance ? simple drive requirement ? low gate charge ? fast switching characteristic ? rohs compliant package symbol outline to-220 mtd07n04e3 ordering information device package shipping MTD07N04E3-0-UB-X to-220 (rohs compliant) 50 pcs/tube, 20 tubes/box, 4 boxes / carton g gate d drain ssource 6.6 m (typ) environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, ub : 50 pcs / tube, 20 tubes/box product rank, zero for no rank products product name g d s
cystech electronics corp. spec. no. : c140e3 issued date : 2015.12.09 revised date : page no. : 2/ 8 mtd07n04e3 cystek product specification absolute maximum ratings (t c =25c) parameter symbol limits unit drain-source voltage (note 1) v ds 40 gate-source voltage v gs 20 v continuous drain current @t c =25 c, v gs =10v (silicon limit) (note 1) 77.4 continuous drain current @t c =25 c, v gs =10v (package limit) (note 1) 58 continuous drain current @t c =100 c, v gs =10v (note 1) i d 49 continuous drain current @t a =25 c, v gs =10v (note 2) 13.4 continuous drain current @t a =70 c, v gs =10v (note 2) i dsm 10.7 pulsed drain current i dm 310 avalanche current i as 51 a single pulse avalanche energy @ l=0.1mh, i d =51 amps, v dd =25v (note 4) e as 130 repetitive avalanche energy (note 3) e ar 7 mj t c =25 c (note 1) 69 t c =100 c (note 1) p d 28 t a =25 c (note 2) 2.1 power dissipation t a =70 c (note 2) p dsm 1.3 w maximum temperature for soldering @ lead at 0.063 in(1.6mm) from case for 10 seconds t l 300 maximum temperature for soldering @ package body for 10 seconds t pkg 260 operating junction and storage temperature tj, tstg -55~+150 c *drain current limited by maximum junction temperature thermal data parameter symbol value unit thermal resistance, junction-to-case, max r jc 1.8 thermal resistance, junction-to-ambient, max (note 2) r ja 60 c/w note : 1 . the power dissipation p d is based on t j(max) =150 c, using junction-to-case thermal resistance, and is more useful in setting the upper di ssipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user?s specific board design. 3. repetitive rating, pulse width limited by junction temperature t j(max) =150 c. 4. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 100% tested by condition of v dd =25v, i d =18a, l=0.5mh, v gs =10v.
cystech electronics corp. spec. no. : c140e3 issued date : 2015.12.09 revised date : page no. : 3/ 8 mtd07n04e3 cystek product specification characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 40 - - v v gs =0v, i d =250 a ? bv dss / ? tj - 29 - mv/ c reference to 25 c, i d =250 a v gs(th) 1.5 - 3.0 v v ds = v gs , i d =250 a *g fs - 18 - s v ds =10v, i d =20a i gss - - 100 na v gs = 20v - - 1 v ds =32v, v gs =0v i dss - - 5 a v ds =32v, v gs =0v, tj=55 c - 5.1 6.7 v gs =10v, i d =20a *r ds(on) - 6.6 9.0 m v gs =4.5v, i d =10a dynamic *qg - 37 - *qgs - 4.7 - *qgd - 12.3 - nc v dd =32v, i d =58a,v gs =10v *t d(on) - 12.4 - *tr - 15.8 - *t d(off) - 44 - *t f - 10.2 - ns v dd =20v, i d =58a, v gs =10v, r g =2.7 ciss - 1421 - coss - 172 - crss - 126 - pf v gs =0v, v ds =25v, f=1mhz source-drain diode *i s - - 58 *i sm - - 310 a *v sd - 0.84 1.2 v i s =20a, v gs =0v *trr - 9.1 - ns *qrr - 3.1 - nc v gs =0v, i f =58a, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c140e3 issued date : 2015.12.09 revised date : page no. : 4/ 8 mtd07n04e3 cystek product specification typical characteristics typical output characteristics 0 20 40 60 80 100 120 140 160 180 200 024681 0 brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v 10v, 9v, 8v v ds , drain-source voltage(v) i d , drain current (a) 7v 6v 5v v gs =3v 4 v 4.5v 3.5v static drain-source on-state resistance vs drain current 1 10 100 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 02468101214161820 i dr , reverse drain current(a) v sd , source-drain voltage(v) tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 10 20 30 40 50 60 70 80 90 100 024681 0 drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =20a r ds( on) @tj=25c : 5.1m typ. v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =20a
cystech electronics corp. spec. no. : c140e3 issued date : 2015.12.09 revised date : page no. : 5/ 8 mtd07n04e3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0 5 10 15 20 25 30 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.2 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =10v v ds =15v gate charge characteristics 0 2 4 6 8 10 0 5 10 15 20 25 30 35 40 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =56a v ds =32v maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) t c =25c, tj=150c v gs =10v, r jc =1.8c/w single pulse dc 100ms r dson limited 10 s 100 s 1ms 10ms maximum drain current vs case temperature 0 10 20 30 40 50 60 70 80 90 25 50 75 100 125 150 175 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =1.8c/w silicon limit package limit
cystech electronics corp. spec. no. : c140e3 issued date : 2015.12.09 revised date : page no. : 6/ 8 mtd07n04e3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 20 40 60 80 100 120 140 160 180 200 0246810 v gs , gate-source voltage(v) i d , drain current(a) v ds =10v single pulse power rating, junction to case 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) power (w) t j(max) =150c t c =25c r jc =1.8c/w transient thermal response curves 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =1.8c/w
cystech electronics corp. spec. no. : c140e3 issued date : 2015.12.09 revised date : page no. : 7/ 8 mtd07n04e3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 5 +1/-1 seconds 260 +0/-5 c recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds ? time(ts min to ts max ) time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c140e3 issued date : 2015.12.09 revised date : page no. : 8/ 8 mtd07n04e3 cystek product specification to-220 dimension *: typical millimeters inches millimeters style: pin 1.gate 2.drain 3.source 4.drain 3-lead to-220 plastic package cystek package code: e3 1 2 3 device name date code d07 n04 marking: inches dim min. max. min. max. dim min. max. min. max. a 4.470 4.670 0.176 0.184 e1 12.060 12.460 0.475 0.491 a1 2.520 2.820 0.099 0.111 e 2.540* 0.100* b 0.710 0.910 0.028 0.036 e1 4.980 5.180 0.196 0.204 b1 1.170 1.370 0.046 0.054 f 2.590 2.890 0.102 0.114 c 0.310 0.530 0.012 0.021 h 0.000 0.300 0.000 0.012 c1 1.170 1.370 0.046 0.054 l 13. 400 13.800 0.528 0.543 d 10.010 10.310 0.394 0.406 l1 3.560 3.960 0.140 0.156 e 8.500 8.900 0.335 0.350 3.735 3.935 0.147 0.155 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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